D12320VF25IV Datasheet, PDF (272/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 7 DMA Controller (Not Supported in the H8S/2321)
7.3.4 DMA Control Register (DMACR)
DMACR is a 16-bit readable/writable register that controls the operation of each DMAC channel.
In full address mode, DMACRA and DMACRB have different functions.
DMACR is initialized to H'0000 by a reset, and in hardware standby mode.
DMACRA
Bit
: 15
14
13
12
11
10
9
8
DTSZ SAID SAIDE BLKDIR BLKE
—
—
—
Initial value :
0
0
0
0
0
0
0
0
R/W
: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DMACRB
Bit
:
7
—
Initial value :
0
R/W
: R/W
6
5
4
DAID DAIDE
—
0
0
0
R/W
R/W
R/W
3
DTF3
0
R/W
2
DTF2
0
R/W
1
DTF1
0
R/W
0
DTF0
0
R/W
Bit 15—Data Transfer Size (DTSZ): Selects the size of data to be transferred at one time.
Bit 15
DTSZ
0
1
Description
Byte-size transfer
Word-size transfer
(Initial value)
Rev.6.00 Sep. 27, 2007 Page 240 of 1268
REJ09B0220-0600