D12320VF25IV Datasheet, PDF (946/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 20 Clock Pulse Generator
Bit 2
SCK2
0
1
Bit 1
SCK1
0
1
0
1
Bit 0
SCK0
0
1
0
1
0
1
—
Description
DIV = 0
DIV = 1
Bus master is in high-speed
Bus master is in high-speed
mode
(Initial value) mode
(Initial value)
Medium-speed clock is φ/2
Clock supplied to entire chip is φ/2
Medium-speed clock is φ/4
Clock supplied to entire chip is φ/4
Medium-speed clock is φ/8
Clock supplied to entire chip is φ/8
Medium-speed clock is φ/16
—
Medium-speed clock is φ/32
—
—
—
20.3 Oscillator
Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock.
20.3.1 Connecting a Crystal Resonator
Circuit Configuration: A crystal resonator can be connected as shown in the example in figure
20.2. Select the damping resistance R_d according to table 20.2. An AT-cut parallel-resonance
crystal should be used.
C_L1
EXTAL
XTAL
R_d
C_L2
C_L1 = C_L2 = 10 to 22 pF
Figure 20.2 Connection of Crystal Resonator (Example)
Table 20.2 Damping Resistance Value
Frequency (MHz)
Rd (Ω)
2
4
8
12
16
20
25
6.8 k 500
200
0
0
0
0
Rev.6.00 Sep. 27, 2007 Page 914 of 1268
REJ09B0220-0600