D12320VF25IV Datasheet, PDF (890/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 19 ROM
19.22.9 Register Configuration
The registers used to control the on-chip flash memory when enabled are shown in table 19.48.
In order to access the FLMCR1, FLMCR2, EBR1, and EBR2 registers, the FLSHE bit must be set
to 1 in SYSCR2 (except RAMER).
Table 19.48 Flash Memory Registers
Register Name
Flash memory control register 1
Flash memory control register 2
Erase block register 1
Erase block register 2
System control register 2
Abbreviation
FLMCR1^*6
FLMCR2^*6
EBR1^*6
EBR2^*6
SYSCR2^*7
R/W
R/W^*3
R/W^*3
R/W^*3
R/W^*3
R/W
Initial Value
H'00/H'80^*4
H'00
H'00^*5
H'00^*5
H'00
Address^*1
H'FFC8^*2
H'FFC9^*2
H'FFCA^*2
H'FFCB^*2
H'FF42
RAM emulation register
RAMER
R/W
H'00
H'FEDB
Notes: 1. Lower 16 bits of the address.
2. Flash memory. Registers selection is performed by the FLSHE bit in system control
register 2 (SYSCR2).
3. In modes in which the on-chip flash memory is disabled, a read will return H'00, and
writes are invalid. Writes are also disabled when the FWE bit is cleared to 0 in
FLMCR1.
4. When a high level is input to the FWE pin, the initial value is H'80.
5. When a low level is input to the FWE pin, or if a high level is input and the SWE1 bit in
FLMCR1 is not set, bits EB11 to EB0 are initialized to 0, and if the SWE2 bit is not set,
bits EB15 to EB12 are initialized to 0.
6. FLMCR1, FLMCR2, EBR1, and EBR2 are 8-bit registers. Only byte accesses are valid
for these registers, the access requiring 2 states.
7. The SYSCR2 register can only be used in the F-ZTAT versions. In the mask ROM
versions this register will return an undefined value if read, and cannot be modified.
Rev.6.00 Sep. 27, 2007 Page 858 of 1268
REJ09B0220-0600