D12320VF25IV Datasheet, PDF (265/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 7 DMA Controller (Not Supported in the H8S/2321)
When DTE = 1 and DTA = 0, the internal interrupt source selected by the data transfer factor
setting is not cleared when a transfer is performed, and can issue an interrupt request to the CPU
or DTC in parallel. In this case, the interrupt source should be cleared by the CPU or DTC
transfer.
When DTE = 0, the internal interrupt source selected by the data transfer factor setting issues an
interrupt request to the CPU or DTC regardless of the DTA bit setting.
Bit 11—Data Transfer Acknowledge 1B (DTA1B): Enables or disables clearing, when DMA
transfer is performed, of the internal interrupt source selected by the channel 1B data transfer
factor setting.
Bit 11
DTA1B
0
1
Description
Clearing of selected internal interrupt source at time of DMA transfer is disabled
(Initial value)
Clearing of selected internal interrupt source at time of DMA transfer is enabled
Bit 10—Data Transfer Acknowledge 1A (DTA1A): Enables or disables clearing, when DMA
transfer is performed, of the internal interrupt source selected by the channel 1A data transfer
factor setting.
Bit 10
DTA1A
0
1
Description
Clearing of selected internal interrupt source at time of DMA transfer is disabled
(Initial value)
Clearing of selected internal interrupt source at time of DMA transfer is enabled
Bit 9—Data Transfer Acknowledge 0B (DTA0B): Enables or disables clearing, when DMA
transfer is performed, of the internal interrupt source selected by the channel 0B data transfer
factor setting.
Bit 9
DTA0B
0
1
Description
Clearing of selected internal interrupt source at time of DMA transfer is disabled
(Initial value)
Clearing of selected internal interrupt source at time of DMA transfer is enabled
Rev.6.00 Sep. 27, 2007 Page 233 of 1268
REJ09B0220-0600