D12320VF25IV Datasheet, PDF (559/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 10 16-Bit Timer Pulse Unit (TPU)
Contention between TGR Write and Input Capture: If the input capture signal is generated in
the T₂ state of a TGR write cycle, the input capture operation takes precedence and the write to
TGR is not performed.
Figure 10.54 shows the timing in this case.
φ
Address
TGR write cycle
T₁
T₂
TGR address
Write signal
Input capture
signal
TCNT
M
TGR
M
Figure 10.54 Contention between TGR Write and Input Capture
Rev.6.00 Sep. 27, 2007 Page 527 of 1268
REJ09B0220-0600