D12320VF25IV Datasheet, PDF (179/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Bus Controller
Name
Symbol I/O
Function
Chip select 6
CS6
Output Strobe signal indicating that area 6 is
selected.
Chip select 7
CS7
Output Strobe signal indicating that area 7 is
selected.
Upper column address strobe CAS^*
Output 2-CAS DRAM upper column address strobe
signal.
Lower column strobe
LCAS^* Output DRAM lower column address strobe signal.
Wait
WAIT
Input
Wait request signal when accessing
external 3-state access space.
Bus request
BREQ
Input
Request signal that releases bus to
external device.
Bus request acknowledge
BACK
Output Acknowledge signal indicating that bus has
been released.
Bus request output
BREQO
Output
External bus request signal used when
internal bus master accesses external
space when external bus is released.
Note: * The DRAM interface and the CAS and LCAS pin functions are not supported in the
H8S/2321.
Rev.6.00 Sep. 27, 2007 Page 147 of 1268
REJ09B0220-0600