D12320VF25IV Datasheet, PDF (484/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 10 16-Bit Timer Pulse Unit (TPU)
Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the input clock edge.
When the input clock is counted using both edges, the input clock period is halved (e.g. φ/4 both
edges = φ/2 rising edge). If phase counting mode is used on channels 1, 2, 4, and 5, this setting is
ignored and the phase counting mode setting has priority.
Bit 4
CKEG1
Bit 3
CKEG0
Description
0
0
Count at rising edge
(Initial value)
1
Count at falling edge
1
—
Count at both edges
Note: Internal clock edge selection is valid when the input clock is φ/4 or slower. This setting is
ignored if the input clock is φ/1, or when overflow/underflow of another channel is selected.
Bits 2 to 0—Time Prescaler 2 to 0 (TPSC2 to TPSC0): These bits select the TCNT counter
clock. The clock source can be selected independently for each channel. Table 10.4 shows the
clock sources that can be set for each channel.
Table 10.4 TPU Clock Sources
Internal Clock
Channel φ/1 φ/4 φ/16 φ/64 φ/256 φ/1024 φ/4096
0
oooo
1
oooo o
2
oooo
o
3
oooo o
o
o
4
oooo
o
5
oooo o
Legend:
o:
Setting
Blank: No setting
Overflow/
External Clock
Underflow
on Another
TCLKA TCLKB TCLKC TCLKD _Channel
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
Rev.6.00 Sep. 27, 2007 Page 452 of 1268
REJ09B0220-0600