D12320VF25IV Datasheet, PDF (192/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Bus Controller
Bit 7—TP Cycle Control (TPC): Selects whether a 1-state or 2-state precharge cycle (T_P) is to be
used when areas 2 to 5 designated as DRAM space are accessed.
Bit 7
TPC
0
1
Description
1-state precharge cycle is inserted
2-state precharge cycle is inserted
(Initial value)
Bit 6—Burst Access Enable (BE): Selects enabling or disabling of burst access to areas 2 to 5
designated as DRAM space. DRAM space burst access is performed in fast page mode.
Bit 6
BE
0
1
Description
Burst disabled (always full access)
For DRAM space access, access in fast page mode
(Initial value)
Bit 5—RAS Down Mode (RCDM): When areas 2 to 5 are designated as DRAM space and
access to DRAM is interrupted, RCDM selects whether the next DRAM access is waited for with
the RAS signal held low (RAS down mode), or the RAS signal is driven high again (RAS up
mode).
Bit 5
RCDM
0
1
Description
DRAM interface: RAS up mode selected
DRAM interface: RAS down mode selected
(Initial value)
Bit 4—Reserved: Only 0 should be written to this bit.
Bits 3 and 2—Multiplex Shift Count 1 and 0 (MXC1, MXC0): These bits select the size of the
shift to the lower half of the row address in row address/column address multiplexing for the
DRAM interface. In burst operation on the DRAM interface, these bits also select the row address
to be used for comparison.
Rev.6.00 Sep. 27, 2007 Page 160 of 1268
REJ09B0220-0600