D12320VF25IV Datasheet, PDF (1108/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Appendix B Internal I/O Registers
9. If the pulse output group 2 and pulse output group 3 output triggers are the same
according to the PCR setting, the NDRH address will be H'FF4C, and if different, the
address of NDRH for group 2 will be H'FF4E, and that for group 3 will be H'FF4C.
Similarly, if the pulse output group 0 and pulse output group 1 output triggers are the
same according to the PCR setting, the NDRL address will be H'FF4D, and if different,
the address of NDRL for group 0 will be H'FF4F, and that for group 1 will be H'FF4D.
10. Only 0 can be written to bits 7 to 5, to clear the flags.
11. For information on writing, see section 13.2.4, Notes on Register Access.
12. Only 0 can be written to bit 7, to clear the flag.
13. Flash memory registers selection is performed by means of the FLSHE bit in system
control register 2 (SYSCR2).
14. In modes in which the on-chip flash memory is disabled, a read will return H'00, and
writes are invalid. Writes are also disabled when the FWE bit in FLMCR1 is cleared
to 0 (except in the H8S/2329B F-ZTAT).
15. In the H8S/2328B F-ZTAT and H8S/2326 F-ZTAT, the initial value when a high level is
input to the FWE is H'80. The initial value in the H8S/2329B F-ZTAT is H'80.
16. In the H8S/2328B F-ZTAT, this register is initialized to H'00 when a low level is input to
the FWE pin, or when a high level is input to the FWE pin when the SWE bit in
FLMCR1 is not set.
In the H8S/2329B F-ZTAT, this register is initialized to H'00 when the SWE bit in
FLMCR1 is not set.
In the H8S/2326 F-ZTAT, bits EB11 to EB0 are initialized to 0 when a low level is input
to the FWE pin, or a high level is input and the SWE1 bit in FLMCR1 is not set. Bits
EB15 to EB12 are initialized to 0 when a low level is input to the FWE pin, or a high
level is input and the SWE2 bit is not set.
17. FLMCR1, FLMCR2, EBR1, and EBR2 are 8-bit registers. Only byte access can be
used on these registers, with the access requiring two states. (Applies to the
H8S/2329B F-ZTAT, H8S/2328B F-ZTAT, and H8S/2326 F-ZTAT.)
18. The SYSCR2 register can only be used in the F-ZTAT versions. In the mask ROM
versions this register will return an undefined value if read, and cannot be written to.
19. Value of bits 3 to 0.
20. The initial value depends on the mode.
21. Value of bits 4 to 0.
22. Valid only in the F-ZTAT versions.
Rev.6.00 Sep. 27, 2007 Page 1076 of 1268
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