D12320VF25IV Datasheet, PDF (295/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 7 DMA Controller (Not Supported in the H8S/2321)
7.5.4 Repeat Mode
Repeat mode can be specified by setting the RPE bit in DMACR to 1, and clearing the DTIE bit to
0. In repeat mode, MAR is updated after each byte or word transfer in response to a single transfer
request, and this is executed the number of times specified in ETCR. On completion of the
specified number of transfers, MAR and ETCRL are automatically restored to their original
settings and operation continues.
One address is specified by MAR, and the other by IOAR. The transfer direction can be specified
by the DTDIR bit in DMACR.
Table 7.8 summarizes register functions in repeat mode.
Table 7.8 Register Functions in Repeat Mode
Function
Register
DTDIR = 0 DTDIR = 1 Initial Setting
Operation
23
MAR
0 Source
address
register
Destination Start address of
address transfer destination
register or transfer source
Incremented/
decremented every
transfer. Initial
setting is restored
when value reaches
H'0000
23
15
H'FF
IOAR
0 Destination Source
address address
register register
Start address of Fixed
transfer source or
transfer destination
7
0 Holds number of
ETCRH ^transfers
Number of transfers Fixed
Transfer counter
7
0
ETCRL
Legend:
MAR: Memory address register
IOAR: I/O address register
ETCR: Execute transfer count register
DTDIR: Data transfer direction bit
Number of transfers Decremented every
transfer. Loaded with
ETCRH value when
count reaches H'00
Rev.6.00 Sep. 27, 2007 Page 263 of 1268
REJ09B0220-0600