D12320VF25IV Datasheet, PDF (147/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 5 Interrupt Controller
5.2.2 Interrupt Priority Registers A to K (IPRA to IPRK)
Bit
:
7
6
5
4
3
—
IPR6 IPR5 IPR4
—
Initial value :
0
1
1
1
0
R/W
:—
R/W
R/W
R/W
—
2
IPR2
1
R/W
1
IPR1
1
R/W
0
IPR0
1
R/W
The IPR registers are eleven 8-bit readable/writable registers that set priorities (levels 7 to 0) for
interrupts other than NMI.
The correspondence between IPR settings and interrupt sources is shown in table 5.3.
The IPR registers set a priority (levels 7 to 0) for each interrupt source other than NMI.
The IPR registers are initialized to H'77 by a reset and in hardware standby mode.
Bits 7 and 3—Reserved: Read-only bits, always read as 0.
Table 5.3 Correspondence between Interrupt Sources and IPR Settings
Bits
Register
6 to 4
2 to 0
IPRA
IRQ0
IRQ1
IPRB
IRQ2
IRQ3
IRQ4
IRQ5
IPRC
IRQ6
IRQ7
DTC
IPRD
IPRE
Watchdog timer
—^*1
Refresh timer
A/D converter
IPRF
TPU channel 0
TPU channel 1
IPRG
TPU channel 2
TPU channel 3
IPRH
TPU channel 4
TPU channel 5
IPRI
IPRJ
8-bit timer channel 0
DMAC^*2
8-bit timer channel 1
SCI channel 0
IPRK
SCI channel 1
SCI channel 2
Notes: 1. Reserved bits.
2. The refresh timer and DMAC are not supported in the H8S/2321.
Rev.6.00 Sep. 27, 2007 Page 115 of 1268
REJ09B0220-0600