D12320VF25IV Datasheet, PDF (432/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 9 I/O Ports
Bit 2—LWR Output Disable (LWROD): Enables or disables LWR output.
Bit 2
LWROD
0
1
Description
PF3 is designated as LWR output pin
(Initial value)
PF3 is designated as I/O port, and does not function as LWR output pin
Bit 1—IRQ Port Switching Select (IRQPAS): Selects switching of input pins for IRQ₄ to IRQ₇.
IRQ₄ to IRQ₇ input is always performed from one of the ports.
Bit 1
IRQPAS
0
1
Description
PA4 to PA7 used for IRQ4 to IRQ7 input
P50 to P53 used for IRQ4 to IRQ7 input
(Initial value)
Bit 0—RAM Enable (RAME): Enables or disables on-chip RAM. The RAME bit is initialized
when the reset state is released. It is not initialized in software standby mode.
Bit 0
RAME
0
1
Description
On-chip RAM disabled
On-chip RAM enabled
(Initial value)
9.8.3 Pin Functions
Port A pins function as address outputs, interrupt input pins (IRQ₄ to IRQ₇), and I/O ports. Port A
pin functions are shown in table 9.14.
Rev.6.00 Sep. 27, 2007 Page 400 of 1268
REJ09B0220-0600