D12320VF25IV Datasheet, PDF (1225/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

TSTR—Timer Start Register
Bit
:
7
6
—
—
Initial value :
0
0
Read/Write : —
—
Appendix B Internal I/O Registers
H'FFC0
TPU
5
CST5
0
R/W
4
CST4
0
R/W
3
CST3
0
R/W
2
CST2
0
R/W
1
CST1
0
R/W
0
CST0
0
R/W
Counter Start
0 TCNTn count operation is stopped
1 TCNTn performs count operation
(n = 5 to 0)
Note:
If 0 is written to the CST bit during operation with the TIOC pin designated for output,
the counter stops but the TIOC pin output compare output level is retained. If TIOR
is written to when the CST bit is cleared to 0, the pin output level will be changed to
the set initial output value.
TSYR—Timer Synchro Register
H'FFC1
Bit
:
7
—
Initial value :
0
Read/Write : —
6
5
4
3
2
1
0
— SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0
0
0
0
0
0
0
0
—
R/W
R/W
R/W
R/W
R/W
R/W
TPU
Timer Synchronization
0 TCNTn operates independently (TCNT presetting/
clearing is unrelated to other channels)
1 TCNTn performs synchronous operation
TCNT synchronous presetting/synchronous clearing
is possible
(n = 5 to 0)
Notes: 1.
2.
To set synchronous operation, the SYNC bits for at least two channels must
be set to 1.
To set synchronous clearing, in addition to the SYNC bit , the TCNT clearing
source must also be set by means of bits CCLR2 to CCLR0 in TCR.
Rev.6.00 Sep. 27, 2007 Page 1193 of 1268
REJ09B0220-0600