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D12320VF25IV Datasheet, PDF (85/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents | |||
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Type
Arithmetic
operations
Instruction
DIVXS
CMP
NEG
EXTU
EXTS
TAS
Section 2 CPU
Size*1
B/W
B/W/L
B/W/L
W/L
W/L
B
Function
Rd ÷ Rs â Rd
Performs signed division on data in two general
registers: either 16 bits ÷ 8 bits â 8-bit quotient and 8-bit
remainder or 32 bits ÷ 16 bits â 16-bit quotient and 16-
bit remainder.
Rd â Rs, Rd â #IMM
Compares data in a general register with data in another
general register or with immediate data, and sets CCR
bits according to the result.
0 â Rd â Rd
Takes the two's complement (arithmetic complement) of
data in a general register.
Rd (zero extension) â Rd
Extends the lower 8 bits of a 16-bit register to word size,
or the lower 16 bits of a 32-bit register to longword size,
by padding with zeros on the left.
Rd (sign extension) â Rd
Extends the lower 8 bits of a 16-bit register to word size,
or the lower 16 bits of a 32-bit register to longword size,
by extending the sign bit.
@ERd â 0, 1 â (<bit 7> of @Erd)*2
Tests memory contents, and sets the most significant bit
(bit 7) to 1.
Rev.6.00 Sep. 27, 2007 Page 53 of 1268
REJ09B0220-0600
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