D12320VF25IV Datasheet, PDF (897/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 19 ROM
Bit 0—Program 2 (P2): Selects program mode transition or clearing for H'040000 to H'07FFFF.
Do not set the SWE2, PSU2, ESU2, EV2, PV2, or E2 bit at the same time.
Bit 0
P2
0
1
Description
Program mode cleared
Transition to program mode
[Setting condition]
When FWE = 1, SWE2 = 1, and PSU2 = 1
(Initial value)
19.23.3 Erase Block Register 1 (EBR1)
Bit
:
7
6
5
4
3
2
1
0
EBR1
EB7
EB6
EB5
EB4
EB3
EB2
EB1
EB0
Initial value :
0
0
0
0
0
0
0
0
R/W
: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is
initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low
level is being input to the FWE pin, and when the SWE1 bit in FLMCR1 is not set when a high
level is being input to the FWE pin. When a bit in EBR1 is set, the corresponding block can be
erased. Other blocks are erase-protected. Set only one bit in EBR1 and EBR2 together (setting
more than one bit will automatically clear all EBR1 and EBR2 bits to 0). When on-chip flash
memory is disabled, a read will return H'00 and writes are invalid.
The flash memory block configuration is shown in table 19.49
Rev.6.00 Sep. 27, 2007 Page 865 of 1268
REJ09B0220-0600