D12320VF25IV Datasheet, PDF (257/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 7 DMA Controller (Not Supported in the H8S/2321)
7.2.2 I/O Address Register (IOAR)
Bit
: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOAR
:
Initial value : * * * * * * * * * * * * * * * *
R/W
: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
*: Undefined
IOAR is a 16-bit readable/writable register that specifies the lower 16 bits of the transfer source
address or destination address. The upper 8 bits of the transfer address are automatically set to
H'FF.
Whether IOAR functions as the source address register or as the destination address register can
be selected by means of the DTDIR bit in DMACR.
IOAR is invalid in single address mode.
IOAR is not incremented or decremented each time a transfer is executed, so the address specified
by IOAR is fixed.
IOAR is not initialized by a reset or in standby mode.
7.2.3 Execute Transfer Count Register (ETCR)
ETCR is a 16-bit readable/writable register that specifies the number of transfers. The setting of
this register is different for sequential mode and idle mode on the one hand, and for repeat mode
on the other.
Sequential Mode and Idle Mode
Transfer Counter (ETCR)
Bit
: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
:
Initial value : * * * * * * * * * * * * * * * *
R/W
: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
*: Undefined
Rev.6.00 Sep. 27, 2007 Page 225 of 1268
REJ09B0220-0600