D12320VF25IV Datasheet, PDF (210/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Bus Controller
16-Bit 3-State Access Space: Figures 6.11 to 6.13 show bus timings for a 16-bit 3-state access
space. When a 16-bit access space is accessed , the upper half (D₁₅ to D₈) of the data bus is used
for the even address, and the lower half (D₇ to D₀) for the odd address.
Wait states can be inserted.
Bus cycle
T₁
T₂
T₃
φ
Address bus
CSn
AS
RD
Read D₁₅ to D₈
Valid
D₇ to D₀
HWR
Write
LWR
D₁₅ to D₈
D₇ to D₀
Note: n = 0 to 7
Invalid
High
Valid
High impedance
Figure 6.11 Bus Timing for 16-Bit 3-State Access Space (1) (Even Address Byte Access)
Rev.6.00 Sep. 27, 2007 Page 178 of 1268
REJ09B0220-0600