D12320VF25IV Datasheet, PDF (315/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 7 DMA Controller (Not Supported in the H8S/2321)
7.5.10 DMAC Bus Cycles (Dual Address Mode)
Short Address Mode: Figure 7.19 shows a transfer example in which TEND output is enabled
and byte-size short address mode transfer (sequential/idle/repeat mode) is performed from external
8-bit, 2-state access space to internal I/O space.
φ
Address bus
RD
HWR
LWR
TEND
DMA
read
DMA
write
DMA
read
DMA
write
DMA
read
DMA DMA
write dead
Bus release
Bus release
Bus release Last transfer
cycle
Bus
release
Figure 7.19 Example of Short Address Mode Transfer
A one-byte or one-word transfer is performed for one transfer request, and after the transfer the
bus is released. While the bus is released one or more bus cycles are executed by the CPU or DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
In repeat mode, when TEND output is enabled, TEND output goes low in the transfer cycle in
which the transfer counter reaches 0.
Rev.6.00 Sep. 27, 2007 Page 283 of 1268
REJ09B0220-0600