D12320VF25IV Datasheet, PDF (461/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

9.13.2 Register Configuration
Table 9.24 shows the port F register configuration.
Table 9.24 Port F Registers
Name
Abbreviation
R/W
Port F data direction register
PFDDR
W
Port F data register
PFDR
R/W
Port F register
PORTF
R
Port function control register 2 PFCR2
R/W
System control register
SYSCR
R/W
Notes: 1. Lower 16 bits of the address.
2. Initial value depends on the mode.
Section 9 I/O Ports
Initial Value
H'80/H'00^*2
H'00
Undefined
H'30
H'01
Address^*1
H'FEBE
H'FF6E
H'FF5E
H'FFAC
H'FF39
Port F Data Direction Register (PFDDR)
Bit
:
7
6
5
4
3
2
1
0
PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR
Modes 4 to 6
Initial value :
1
0
0
0
0
0
0
0
R/W
:W
W
W
W
W
W
W
W
Mode 7
Initial value :
0
0
0
0
0
0
0
0
R/W
:W
W
W
W
W
W
W
W
PFDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port F. PFDDR cannot be read; if it is, an undefined value will be read.
PFDDR is initialized by a reset, and in hardware standby mode, to H'80 in modes 4 to 6, and to
H'00 in mode 7. It retains its prior state in software standby mode. The OPE bit in SBYCR is used
to select whether the bus control output pins retain their output state or become high-impedance
when a transition is made to software standby mode.
Rev.6.00 Sep. 27, 2007 Page 429 of 1268
REJ09B0220-0600