D12320VF25IV Datasheet, PDF (194/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Bus Controller
6.2.7 DRAM Control Register (DRAMCR)
Bit
:
Initial value :
R/W
:
7
RFSHE
0
R/W
6
RCW
0
R/W
5
RMODE
0
R/W
4
CMF
0
R/W
3
CMIE
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
DRAMCR is an 8-bit readable/writable register that selects the DRAM refresh mode and refresh
counter clock, and controls the refresh timer.
DRAMCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Note: In the H8S/2321 this register is reserved and must not be accessed.
Bit 7—Refresh Control (RFSHE): Selects whether or not refresh control is performed. When
refresh control is not performed, the refresh timer can be used as an interval timer.
Bit 7
RFSHE
0
1
Description
Refresh control is not performed
Refresh control is performed
(Initial value)
Bit 6—RAS-CAS Wait (RCW): Controls wait state insertion in DRAM interface CAS-before-
RAS refreshing.
Bit 6
RCW
0
1
Description
Wait state insertion in CAS-before-RAS refreshing disabled
RAS falls in TRr cycle
One wait state inserted in CAS-before-RAS refreshing
RAS falls in TRc1 cycle
(Initial value)
Bit 5—Refresh Mode (RMODE): When refresh control is performed (RFSHE = 1), selects
whether or not self-refresh control is performed in software standby mode.
Bit 5
RMODE
0
1
Description
Self-refreshing is not performed in software standby mode
Self-refreshing is performed in software standby mode
(Initial value)
Rev.6.00 Sep. 27, 2007 Page 162 of 1268
REJ09B0220-0600