D12320VF25IV Datasheet, PDF (1223/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

TCSR—Timer Control/Status Register
Bit
:
7
OVF
Initial value :
0
Read/Write^*1: _R/(W)*²
6
WT/IT
0
R/W
5
TME
0
R/W
Appendix B Internal I/O Registers
H'FFBC (W), H'FFBC (R)
WDT
4
3
2
1
0
—
—
CKS2 CKS1 CKS0
1
1
0
0
0
—
—
R/W
R/W
R/W
Clock Select
CKS2 CKS1 CKS0 Clock
Overflow period*
(when φ = 20 MHz)
0
0
0 φ/2 (Initial value) 25.6 µs
1 φ/64
819.2 µs
1
0 φ/128
1.6 ms
1 φ/512
6.6 ms
1
0
0 φ/2048
26.2 ms
1 φ/8192
104.9 ms
1
0 φ/32768
419.4 ms
1 φ/131072
1.68 s
Note: * The overflow period is the time from when TCNT
starts counting up from H'00 until overflow occurs.
Timer Enable
0 TCNT is initialized to H'00 and halted
1 TCNT counts
Timer Mode Select
0 Interval timer mode: Sends the CPU an interval timer interrupt
request (WOVI) when TCNT overflows
1 Watchdog timer mode: Generates the WDTOVF signal^*1 when
TCNT overflows^*2
Notes: 1. The WDTOVF pin function is not available in the F-ZTAT versions.
2. For details of the case where TCNT overflows in watchdog timer
mode, see section 13.2.3, Reset Control/Status Register (RSTCSR).
Overflow Flag
0 [Clearing condition]
When 0 is written to OVF after reading OVF = 1
1 [Setting condition]
When TCNT overflows from H'FF to H'00 in interval timer mode
Notes: 1. The method for writing to TCSR is different from that for general registers to prevent
accidental overwriting. For details, see section 13.2.4, Notes on Register Access.
2. Can only be written with 0 for flag clearing.
Rev.6.00 Sep. 27, 2007 Page 1191 of 1268
REJ09B0220-0600