D12320VF25IV Datasheet, PDF (241/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Bus Controller
6.9 Write Data Buffer Function
The chip has a write data buffer function in the external data bus. Using the write data buffer
function enables external writes and DMA single address mode transfers to be executed in parallel
with internal accesses. The write data buffer function is made available by setting the WDBE bit
in BCRL to 1.
Figure 6.36 shows an example of the timing when the write data buffer function is used. When this
function is used, if an external write or DMA single address mode transfer* continues for 2 states
or longer, and there is an internal access next, only an external write is executed in the first state,
but from the next state onward an internal access (on-chip memory or internal I/O register
read/write) is executed in parallel with the external write rather than waiting until it ends.
Note: * The DMAC is not supported in the H8S/2321.
On-chip memory read Internal I/O register read
External write cycle
T₁
T₂
T_W
T_W
T₃
Internal address bus
Internal read signal
Internal memory Internal I/O register address
A₂₃ to A₀
External
space
write
CSn
HWR, LWR
External address
D₁₅ to D₀
Note: n = 0 to 7
Figure 6.36 Example of Timing when Write Data Buffer Function is Used
Rev.6.00 Sep. 27, 2007 Page 209 of 1268
REJ09B0220-0600