D12320VF25IV Datasheet, PDF (251/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 7 DMA Controller (Not Supported in the H8S/2321)
7.1.3 Overview of Functions
Tables 7.1 (1) and (2) summarize DMAC functions in short address mode and full address mode,
respectively.
Table 7.1 (1) Overview of DMAC Functions (Short Address Mode)
Address Register Bit Length
Transfer Mode
Transfer Source Source
Destination
Dual address mode
• TPU channel 0 to 24/16
• Sequential mode
5 compare
⎯ 1-byte or 1-word transfer executed
match/input
for one transfer request
capture A
⎯ Memory address
interrupt
incremented/decremented by 1 or 2 ^{• SCI transmit-}
⎯ 1 to 65,536 transfers
data-empty
interrupt
• Idle mode
• SCI receive-
⎯ 1-byte or 1-word transfer executed
data-full interrupt
for one transfer request
• A/D converter
⎯ Memory address fixed
conversion end
⎯ 1 to 65,536 transfers
interrupt
• Repeat mode
• External request
⎯ 1-byte or 1-word transfer executed
for one transfer request
16/24
⎯ Memory address incremented/
decremented by 1 or 2
⎯ After specified number of transfers
(1 to 256), initial state is restored
and operation continues
• Single address mode
• External request 24/DACK
DACK/24
• 1-byte or 1-word transfer executed for
one transfer request
• Transfer in 1 bus cycle using DACK pin
in place of address specifying I/O
• Specifiable for sequential, idle, and
repeat modes
Rev.6.00 Sep. 27, 2007 Page 219 of 1268
REJ09B0220-0600