D12320VF25IV Datasheet, PDF (104/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 2 CPU
Advanced mode
SP
CCR
PC
(24 bits)
SP
EXR
Reserved*
CCR
PC
(24 bits)
(c) Interrupt control mode 0
Note: * Ignored when returning.
(d) Interrupt control mode 2
Figure 2.13 Stack Structure after Exception Handling (Examples)
2.8.4 Program Execution State
In this state the CPU executes program instructions in sequence.
2.8.5 Bus-Released State
This is a state in which the bus has been released in response to a bus request from a bus master
other than the CPU. While the bus is released, the CPU halts.
There is one other bus master in addition to the CPU: the DMA controller (DMAC)* and data
transfer controller (DTC).
For further details, refer to section 6, Bus Controller.
Note: * The DMAC is not supported in the H8S/2321.
Rev.6.00 Sep. 27, 2007 Page 72 of 1268
REJ09B0220-0600