D12320VF25IV Datasheet, PDF (1112/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Appendix B Internal I/O Registers
TCR3—Timer Control Register 3
H'FE80
Bit
:
Initial value :
Read/Write :
7
CCLR2
0
R/W
6
5
4
3
2
CCLR1 CCLR0 CKEG1 CKEG0 TPSC2
0
0
0
0
0
R/W R/W R/W R/W R/W
1
TPSC1
0
R/W
0
TPSC0
0
R/W
TPU3
Timer Prescaler
0 0 0 Internal clock: counts on φ/1
1 Internal clock: counts on φ/4
1 0 Internal clock: counts on φ/16
1 Internal clock: counts on φ/64
1 0 0 External clock: counts on TCLKA pin input
1 Internal clock: counts on φ/1024
1 0 Internal clock: counts on φ/256
1 Internal clock: counts on φ/4096
Clock Edge
0 0 Count at rising edge
1 Count at falling edge
Counter Clear
1 — Count at both edges
0 0 0 TCNT clearing disabled
1 TCNT cleared by TGRA compare match/input capture
1 0 TCNT cleared by TGRB compare match/input capture
1 _{TCNT cleared by counter clearing for another channel}
performing synchronous clearing/synchronous operation ^*1
1 0 0 TCNT clearing disabled
1 TCNT cleared by TGRC compare match/input capture ^*2
1 0 TCNT cleared by TGRD compare match/input capture ^*2
1 _{TCNT cleared by counter clearing for another channel}
performing synchronous clearing/synchronous operation ^*1
Notes: 1. Synchronous operation setting is performed by setting the SYNC
bit in TSYR to 1.
2. When TGRC or TGRD is used as a buffer register, TCNT is not
cleared because the buffer register setting has priority, and
compare match/input capture does not occur.
Rev.6.00 Sep. 27, 2007 Page 1080 of 1268
REJ09B0220-0600