D12320VF25IV Datasheet, PDF (152/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 5 Interrupt Controller
IRQnSCA, IRQnSCB
IRQnE
IRQn input
Edge/level
detection circuit
IRQnF
S
Q
R
IRQn interrupt
request
Clear signal
Note: n = 7 to 0
Figure 5.2 Block Diagram of Interrupts IRQ7 to IRQ0
Figure 5.3 shows the timing of setting IRQnF.
φ
IRQn
input pin
IRQnF
Figure 5.3 Timing of Setting IRQnF
The vector numbers for IRQ7 to IRQ0 interrupt exception handling are 23 to 16.
Detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been set for
input or output. Therefore, when a pin is used as an external interrupt input pin, do not clear the
corresponding DDR bit to 0 and use the pin as an I/O pin for another function. The pins that can
be used for IRQ4 to IRQ7 interrupt input can be switched by means of the IRQPAS bit in SYSCR.
Rev.6.00 Sep. 27, 2007 Page 120 of 1268
REJ09B0220-0600