D12320VF25IV Datasheet, PDF (282/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 7 DMA Controller (Not Supported in the H8S/2321)
7.4 Register Descriptions (3)
7.4.1 DMA Write Enable Register (DMAWER)
The DMAC can activate the DTC with a transfer end interrupt, rewrite the channel on which the
transfer ended using a DTC chain transfer, and reactivate the DTC. DMAWER applies restrictions
so that specific bits of DMACR for the specific channel, and also DMATCR and DMABCR, can
be changed to prevent inadvertent rewriting of registers other than those for the channel
concerned. The restrictions applied by DMAWER are valid for the DTC.
Figure 7.2 shows the transfer areas for activating the DTC with a channel 0A transfer end
interrupt, and reactivating channel 0A. The address register and count register area is re-set by the
first DTC transfer, then the control register area is re-set by the second DTC chain transfer.
When re-setting the control register area, perform masking by setting bits in DMAWER to prevent
modification of the contents of the other channels.
DTC
First transfer area
MAR0A
IOAR0A
ETCR0A
MAR0B
IOAR0B
ETCR0B
MAR1A
IOAR1A
ETCR1A
MAR1B
Second transfer area
using chain transfer
IOAR1B
ETCR1B
DMAWER
DMATCR
DMACR0A DMACR0B
DMACR1A DMACR1B
DMABCR
Figure 7.2 Areas for Register Re-Setting by DTC (Example: Channel 0A)
Rev.6.00 Sep. 27, 2007 Page 250 of 1268
REJ09B0220-0600