D12320VF25IV Datasheet, PDF (1006/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 22 Electrical Characteristics
(5) Timing of On-Chip Supporting Modules
Table 22.19 Timing of On-Chip Supporting Modules
Condition B: V_CC = 3.0 V to 3.6 V, AV_CC = 3.0 V to 3.6 V, V_ref = 3.0 V to AV_CC, V_SS = AV_SS =
0 V, φ = 2 MHz to 25 MHz, T_a = –20°C to 75°C (regular specifications),
T_a = –40°C to 85°C (wide-range specifications)
Item
I/O ports
PPG
TPU
8-bit timer
SCI
A/D
converter
Output data delay time
Input data setup time
Input data hold time
Pulse output delay time
Timer output delay time
Timer input setup time
Timer clock input setup time
Timer clock
pulse width
Single-edge
specification
Both-edge
specification
Timer output delay time
Timer reset input setup time
Timer clock input setup time
Timer clock
pulse width
Single-edge
specification
Both-edge
specification
Input clock
cycle
Asynchronous
Synchronous
Input clock pulse width
Input clock rise time
Input clock fall time
Transmit data delay time
Receive data setup time
(synchronous)
Receive data hold time
(synchronous)
Trigger input setup time
Symbol
tPWD
tPRS
tPRH
tPOD
tTOCD
tTICS
tTCKS
tTCKWH
tTCKWL
tTMOD
tTMRS
tTMCS
tTMCWH
tTMCWL
tScyc
tSCKW
tSCKr
tSCKf
tTXD
tRXS
tRXH
tTRGS
Condition B
Min
Max
—
40
25
—
25
—
—
40
—
40
25
—
25
—
1.5
—
2.5
—
—
40
25
—
25
—
1.5
—
2.5
—
4
—
6
—
0.4
0.6
—
1.5
—
1.5
—
40
40
—
40
—
30
—
Unit Test Conditions
ns
Figure 22.20
ns
Figure 22.21
ns
Figure 22.22
ns
Figure 22.23
tcyc
ns
Figure 22.24
ns
Figure 22.26
ns
Figure 22.25
tcyc
tcyc
Figure 22.28
tScyc
tcyc
ns
Figure 22.29
ns
ns
ns
Figure 22.30
Rev.6.00 Sep. 27, 2007 Page 974 of 1268
REJ09B0220-0600