D12320VF25IV Datasheet, PDF (18/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

7.2.4 DMA Control Register (DMACR) ...................................................................... 227
7.2.5 DMA Band Control Register (DMABCR) .......................................................... 231
7.3 Register Descriptions (2) (Full Address Mode) ................................................................ 237
7.3.1 Memory Address Register (MAR)....................................................................... 237
7.3.2 I/O Address Register (IOAR) .............................................................................. 237
7.3.3 Execute Transfer Count Register (ETCR) ........................................................... 238
7.3.4 DMA Control Register (DMACR) ...................................................................... 240
7.3.5 DMA Band Control Register (DMABCR) .......................................................... 244
7.4 Register Descriptions (3) .................................................................................................. 250
7.4.1 DMA Write Enable Register (DMAWER) .......................................................... 250
7.4.2 DMA Terminal Control Register (DMATCR)..................................................... 253
7.4.3 Module Stop Control Register (MSTPCR) .......................................................... 254
7.5 Operation........................................................................................................................... 255
7.5.1 Transfer Modes .................................................................................................... 255
7.5.2 Sequential Mode .................................................................................................. 257
7.5.3 Idle Mode............................................................................................................. 260
7.5.4 Repeat Mode ........................................................................................................ 263
7.5.5 Single Address Mode........................................................................................... 267
7.5.6 Normal Mode....................................................................................................... 270
7.5.7 Block Transfer Mode ........................................................................................... 273
7.5.8 DMAC Activation Sources .................................................................................. 279
7.5.9 Basic DMAC Bus Cycles..................................................................................... 282
7.5.10 DMAC Bus Cycles (Dual Address Mode)........................................................... 283
7.5.11 DMAC Bus Cycles (Single Address Mode) ........................................................ 291
7.5.12 Write Data Buffer Function ................................................................................. 297
7.5.13 DMAC Multi-Channel Operation ........................................................................ 298
7.5.14 Relation Between the DMAC and External Bus Requests, Refresh Cycles,
and the DTC......................................................................................................... 300
7.5.15 NMI Interrupts and DMAC.................................................................................. 301
7.5.16 Forced Termination of DMAC Operation............................................................ 302
7.5.17 Clearing Full Address Mode ................................................................................ 303
7.6 Interrupts ........................................................................................................................... 304
7.7 Usage Notes ...................................................................................................................... 305
Section 8 Data Transfer Controller....................................................................311
8.1 Overview........................................................................................................................... 311
8.1.1 Features................................................................................................................ 311
8.1.2 Block Diagram ..................................................................................................... 312
8.1.3 Register Configuration......................................................................................... 313
8.2 Register Descriptions ........................................................................................................ 314
Rev.6.00 Sep. 27, 2007 Page xvi of xxx
REJ09B0220-0600