D12320VF25IV Datasheet, PDF (200/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Bus Controller
6.3.4 Advanced Mode
The initial state of each area is basic bus interface, 3-state access space. The initial bus width is
selected according to the operating mode. The bus specifications described here cover basic items
only, and the sections on each memory interface (6.4, Basic Bus Interface, 6.5, DRAM Interface
(Not supported in the H8S/2321), and 6.7, Burst ROM Interface) should be referred to for further
details.
Area 0: Area 0 includes on-chip ROM*¹, and in ROM-disabled expansion mode, all of area 0 is
external space. In the ROM-enabled expansion mode, the space excluding on-chip ROM*¹ is
external space.
When area 0 external space is accessed, the CS0 signal can be output.
Either basic bus interface or burst ROM interface can be selected for area 0.
Areas 1 and 6: In external expansion mode, all of area 1 and area 6 is external space.
When area 1 and 6 external space is accessed, the CS1 and CS6 pin signals respectively can be
output.
Only the basic bus interface can be used for areas 1 and 6.
Areas 2 to 5: In external expansion mode, all of area 2 to area 5 is external space.
When area 2 to 5 external space is accessed, signals CS2 to CS5 can be output.
Basic bus interface or DRAM interface*² can be selected for areas 2 to 5. With the DRAM
interface*², signals CS2 to CS5 are used as RAS signals.
Area 7: Area 7 includes the on-chip RAM and internal I/O registers. In external expansion mode,
the space excluding the on-chip RAM and internal I/O registers is external space. The on-chip
RAM is enabled when the RAME bit in the system control register (SYSCR) is set to 1; when the
RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes
external space .
When area 7 external space is accessed, the CS7 signal can be output.
Only the basic bus interface can be used for the area 7 memory interface.
Notes: 1. Only applies to versions with ROM.
2. The DRAM interface is not supported in the H8S/2321.
Rev.6.00 Sep. 27, 2007 Page 168 of 1268
REJ09B0220-0600