D12320VF25IV Datasheet, PDF (292/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 7 DMA Controller (Not Supported in the H8S/2321)
7.5.3 Idle Mode
Idle mode can be specified by setting the RPE bit and DTIE bit in DMACR to 1. In idle mode, one
byte or word is transferred in response to a single transfer request, and this is executed the number
of times specified in ETCR.
One address is specified by MAR, and the other by IOAR. The transfer direction can be specified
by the DTDIR bit in DMACR.
Table 7.7 summarizes register functions in idle mode.
Table 7.7 Register Functions in Idle Mode
Function
Register
DTDIR = 0 DTDIR = 1 Initial Setting
Operation
23
MAR
0 Source
address
register
Destination Start address of Fixed
address transfer destination
register or transfer source
23
15
H'FF
IOAR
0 Destination Source
address address
register register
Start address of Fixed
transfer source or
transfer destination
15
0 Transfer counter
ETCR
Number of transfers Decremented every
transfer; transfer
ends when count
reaches H'0000
Legend:
MAR: Memory address register
IOAR: I/O address register
ETCR: Execute transfer count register
DTDIR: Data transfer direction bit
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is
neither incremented nor decremented each time a byte or word is transferred.
IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of
H'FF.
Rev.6.00 Sep. 27, 2007 Page 260 of 1268
REJ09B0220-0600