D12320VF25IV Datasheet, PDF (767/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 19 ROM
Section 19 ROM
19.1 Overview
The Series has 512, 384, or 256 kbytes of on-chip flash memory, or 256, 128, or 32 kbytes of on-
chip mask ROM. The ROM is connected to the bus master via a 16-bit data bus, enabling both
byte and word data to be accessed in one state. Instruction fetching is thus speeded up, and
processing speed increased.
The on-chip ROM is enabled and disabled by means of the mode pins (MD2 to MD0) and the
EAE bit in BCRL.
The flash memory version of the chip can be erased and programmed with a PROM programmer,
as well as on-board.
19.1.1 Block Diagram
Figure 19.1 shows a block diagram of 256 kbytes of on-chip ROM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'000000
H'000002
H'000001
H'000003
H'03FFFE
H'03FFFF
Figure 19.1 Block Diagram of ROM (256 kbytes)
Rev.6.00 Sep. 27, 2007 Page 735 of 1268
REJ09B0220-0600