D12320VF25IV Datasheet, PDF (1114/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Appendix B Internal I/O Registers
TIOR3H—Timer I/O Control Register 3H
H'FE82
Bit
:
Initial value :
Read/Write :
7
IOB3
0
R/W
6
IOB2
0
R/W
5
IOB1
0
R/W
4
IOB0
0
R/W
3
IOA3
0
R/W
2
IOA2
0
R/W
1
IOA1
0
R/W
0
IOA0
0
R/W
TPU3
TGR3A I/O Control
0 0 0 0 TGR3A Output disabled
1
1
0
is output
compare
register
Initial output is
0 output
0 output at compare match
1 output at compare match
1
Toggle output at compare match
100
Output disabled
1
10
Initial output is
1 output
0 output at compare match
1 output at compare match
1
Toggle output at compare match
1 0 0 0 TGR3A Capture input
is input source is
1 _{capture TIOCA3 pin}
1 * ^register
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
1**
Capture input
Input capture at TCNT4 count-up/
source is channel
4/count clock
count-down
* : Don’t care
TGR3B I/O Control
0 0 0 0 TGR3B Output disabled
1
is output
compare
Initial output is
1 0 ^{register 0 output}
0 output at compare match
1 output at compare match
1
Toggle output at compare match
100
Output disabled
1
10
Initial output is 1 0 output at compare match
output
1 output at compare match
1
Toggle output at compare match
1 0 0 0 TGR3B Capture input
is input source is
1 _{capture TIOCB3 pin}
1 * ^register
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
1**
Capture input _{Input capture at TCNT4 count-up/}
source is channel
4/count clock
count-down^*1
* : Don’t care
Note: 1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000, and φ/1 is used as
the TCNT4 count clock, this setting is invalid and input capture does not
occur.
Rev.6.00 Sep. 27, 2007 Page 1082 of 1268
REJ09B0220-0600