D12320VF25IV Datasheet, PDF (256/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 7 DMA Controller (Not Supported in the H8S/2321)
7.2.1 Memory Address Registers (MAR)
Bit
: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
:— — — — — — — —
Initial value : 0 0 0 0 0 0 0 0 * * * * * * * *
R/W
: — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W
Bit
: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
:
Initial value : * * * * * * * * * * * * * * * *
R/W
: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
*: Undefined
MAR is a 32-bit readable/writable register that specifies the transfer source address or destination
address.
The upper 8 bits of MAR are reserved: they are always read as 0, and cannot be modified.
Whether MAR functions as the source address register or as the destination address register can be
selected by means of the DTDIR bit in DMACR.
MAR is incremented or decremented each time a byte or word transfer is executed, so that the
address specified by MAR is constantly updated. For details, see section 7.2.4, DMA Control
Register (DMACR).
MAR is not initialized by a reset or in standby mode.
Rev.6.00 Sep. 27, 2007 Page 224 of 1268
REJ09B0220-0600