D12320VF25IV Datasheet, PDF (560/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 10 16-Bit Timer Pulse Unit (TPU)
Contention between Buffer Register Write and Input Capture: If the input capture signal is
generated in the T₂ state of a buffer write cycle, the buffer operation takes precedence and the
write to the buffer register is not performed.
Figure 10.55 shows the timing in this case.
φ
Address
Write signal
Input capture
signal
TCNT
Buffer register write cycle
T₁
T₂
Buffer register
address
N
TGR
M
N
Buffer
M
register
Figure 10.55 Contention between Buffer Register Write and Input Capture
Rev.6.00 Sep. 27, 2007 Page 528 of 1268
REJ09B0220-0600