D12320VF25IV Datasheet, PDF (318/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 7 DMA Controller (Not Supported in the H8S/2321)
Full Address Mode (Block Transfer Mode): Figure 7.22 shows a transfer example in which
TEND output is enabled and word-size full address mode transfer (block transfer mode) is
performed from internal 16-bit, 1-state access space to external 16-bit, 2-state access space.
DMA DMA DMA DMA DMA
read write read write dead
DMA DMA DMA DMA DMA
read write read write dead
φ
Address bus
RD
HWR
LWR
TEND
Bus release
Block transfer
Bus release
Last block transfer
Bus
release
Figure 7.22 Example of Full Address Mode (Block Transfer Mode) Transfer
A one-block transfer is performed for one transfer request, and after the transfer the bus is
released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.
In the transfer end cycle of each block (the cycle in which the transfer counter reaches 0), a one-
state DMA dead cycle is inserted after the DMA write cycle.
One block is transmitted without interruption. NMI generation does not affect block transfer
operation.
Rev.6.00 Sep. 27, 2007 Page 286 of 1268
REJ09B0220-0600