D12320VF25IV Datasheet, PDF (377/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 8 Data Transfer Controller
8.5 Usage Notes
Module Stop: When the MSTP14 bit in MSTPCR is set to 1, the DTC clock stops, and the DTC
enters the module stop state. However, 1 cannot be written to the MSTP14 bit while the DTC is
operating.
On-Chip RAM: The MRA, MRB, SAR, DAR, CRA, and CRB registers are all located in on-chip
RAM. When the DTC is used, the RAME bit in SYSCR must not be cleared to 0.
DMAC Transfer End Interrupt^*: When DTC transfer is activated by a DMAC transfer end
interrupt, regardless of the transfer counter and DISEL bit, the DMAC’s DTE bit is not subject to
DTC control, and the write data has priority. Consequently, an interrupt request may not be sent to
the CPU when the DTC transfer counter reaches 0.
Note: * The DMAC is not supported in the H8S/2321.
DTCE Bit Setting: For DTCE bit setting, read/write operations must be performed using bit-
manipulation instructions such as BSET and BCLR. For the initial setting only, however, when
multiple activation sources are set at one time, it is possible to disable interrupts and write after
executing a dummy read on the relevant register.
Chain Transfer: When chain transfer is used, clearing of the activation source or DTCER is
performed when the last of the chain of data transfers is executed. SCI and A/D converter
interrupt/activation sources, on the other hand, are cleared when the DTC reads or writes to the
prescribed register.
Therefore, when the DTC is activated by an interrupt or activation source, if a read/write of the
relevant register is not included in the last chained data transfer, the interrupt or activation source
will be retained.
Rev.6.00 Sep. 27, 2007 Page 345 of 1268
REJ09B0220-0600