D12320VF25IV Datasheet, PDF (606/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 12 8-Bit Timers
12.6 Usage Notes
Note that the following kinds of contention can occur in the 8-bit timer module.
12.6.1 Contention between TCNT Write and Clear
If a timer counter clock pulse is generated during the T₂ state of a TCNT write cycle, the clear
takes priority, so that the counter is cleared and the write is not performed.
Figure 12.10 shows this operation.
TCNT write cycle by CPU
T₁
T₂
φ
Address
TCNT address
Internal write signal
Counter clear signal
TCNT
N
H'00
Figure 12.10 Contention between TCNT Write and Clear
Rev.6.00 Sep. 27, 2007 Page 574 of 1268
REJ09B0220-0600