D12320VF25IV Datasheet, PDF (558/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 10 16-Bit Timer Pulse Unit (TPU)
Contention between TGR Read and Input Capture: If the input capture signal is generated in
the T₁ state of a TGR read cycle, the data that is read will be the data after input capture transfer.
Figure 10.53 shows the timing in this case.
φ
Address
TGR read cycle
T₁
T₂
TGR address
Read signal
Input capture
signal
TGR
X
M
Internal
M
data bus
Figure 10.53 Contention between TGR Read and Input Capture
Rev.6.00 Sep. 27, 2007 Page 526 of 1268
REJ09B0220-0600