D12320VF25IV Datasheet, PDF (15/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

4.1.2 Exception Handling Operation............................................................................. 102
4.1.3 Exception Vector Table ....................................................................................... 102
4.2 Reset.................................................................................................................................. 104
4.2.1 Overview.............................................................................................................. 104
4.2.2 Reset Sequence .................................................................................................... 104
4.2.3 Interrupts after Reset............................................................................................ 105
4.2.4 State of On-Chip Supporting Modules after Reset Release ................................. 105
4.3 Traces................................................................................................................................ 106
4.4 Interrupts ........................................................................................................................... 107
4.5 Trap Instruction................................................................................................................. 108
4.6 Stack Status after Exception Handling.............................................................................. 108
4.7 Notes on Use of the Stack ................................................................................................. 109
Section 5 Interrupt Controller ............................................................................111
5.1 Overview........................................................................................................................... 111
5.1.1 Features................................................................................................................ 111
5.1.2 Block Diagram ..................................................................................................... 112
5.1.3 Pin Configuration................................................................................................. 113
5.1.4 Register Configuration......................................................................................... 113
5.2 Register Descriptions ........................................................................................................ 114
5.2.1 System Control Register (SYSCR) ...................................................................... 114
5.2.2 Interrupt Priority Registers A to K (IPRA to IPRK) ............................................ 115
5.2.3 IRQ Enable Register (IER) .................................................................................. 116
5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 117
5.2.5 IRQ Status Register (ISR).................................................................................... 118
5.3 Interrupt Sources ............................................................................................................... 119
5.3.1 External Interrupts ............................................................................................... 119
5.3.2 Internal Interrupts................................................................................................. 121
5.3.3 Interrupt Exception Vector Table ........................................................................ 121
5.4 Interrupt Operation............................................................................................................ 127
5.4.1 Interrupt Control Modes and Interrupt Operation ................................................ 127
5.4.2 Interrupt Control Mode 0 ..................................................................................... 130
5.4.3 Interrupt Control Mode 2 ..................................................................................... 132
5.4.4 Interrupt Exception Handling Sequence .............................................................. 134
5.4.5 Interrupt Response Times .................................................................................... 136
5.5 Usage Notes ...................................................................................................................... 137
5.5.1 Contention between Interrupt Generation and Disabling..................................... 137
5.5.2 Instructions that Disable Interrupts ...................................................................... 138
5.5.3 Times when Interrupts Are Disabled ................................................................... 138
5.5.4 Interrupts during Execution of EEPMOV Instruction.......................................... 138
Rev.6.00 Sep. 27, 2007 Page xiii of xxx
REJ09B0220-0600