D12320VF25IV Datasheet, PDF (355/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 8 Data Transfer Controller
Table 8.2 Chain Transfer Conditions
1st Transfer
CHNE CHNS DISEL CR
0
—
0
Not 0
0
—
0
0
0
—
1
—
1
0
—
—
1
1
0
Not 0
1
1
—
0
1
1
1
Not 0
2nd Transfer
CHNE CHNS DISEL CR
—
—
—
—
—
—
—
—
—
—
—
—
0
—
0
Not 0
0
—
0
0
0
—
1
—
—
—
—
—
0
—
0
Not 0
0
—
0
0
0
—
1
—
—
—
—
—
DTC Transfer
Ends at 1st transfer
Ends at 1st transfer
Interrupt request to CPU
Ends at 2nd transfer
Ends at 2nd transfer
Interrupt request to CPU
Ends at 1st transfer
Ends at 2nd transfer
Ends at 2nd transfer
Interrupt request to CPU
Ends at 1st transfer
Interrupt request to CPU
The DTC transfer mode can be normal mode, repeat mode, or block transfer mode.
The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the
transfer destination address. After each transfer, SAR and DAR are independently incremented,
decremented, or left fixed.
Table 8.3 outlines the functions of the DTC.
Rev.6.00 Sep. 27, 2007 Page 323 of 1268
REJ09B0220-0600