D12320VF25IV Datasheet, PDF (80/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 2 CPU
2.6 Instruction Set
2.6.1 Overview
The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in
table 2.1.
Table 2.1 Instruction Classification
Function
Instructions
Size Types
Data transfer
MOV
POP^*1, PUSH^*1
BWL 5
WL
LDM, STM
L
MOVFPE, MOVTPE^*3
B
Arithmetic
operations
ADD, SUB, CMP, NEG
ADDX, SUBX, DAA, DAS
BWL 19
B
INC, DEC
BWL
ADDS, SUBS
L
MULXU, DIVXU, MULXS, DIVXS
BW
EXTU, EXTS
WL
TAS^*4
B
Logic operations AND, OR, XOR, NOT
BWL 4
Shift
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BWL 8
Bit manipulation BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, B
14
BIAND, BOR, BIOR, BXOR, BIXOR
Branch
Bcc^*2, JMP, BSR, JSR, RTS
—
5
System control
TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP —
9
Block data transfer EEPMOV
—
1
Total: 65
Legend:
B: Byte
W: Word
L: Longword
Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn,
@-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L
ERn, @-SP.
2. Bcc is the general name for conditional branch instructions.
3. Cannot be used in the H8S/2329 Group and H8S/2328 Group.
4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
Rev.6.00 Sep. 27, 2007 Page 48 of 1268
REJ09B0220-0600