D12320VF25IV Datasheet, PDF (949/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 20 Clock Pulse Generator
Table 20.4 External Clock Input Conditions
VCC = 2.7 V
to 3.6 V
Item
Symbol Min Max
External clock input
tEXL
low pulse width
20 —
External clock input
tEXH
high pulse width
20 —
External clock rise time tEXr
External clock fall time tEXf
Clock low pulse width tCL
level
—5
—5
0.4 0.6
80 —
Clock high pulse width tCH
level
0.4 0.6
80 —
VCC = 3.0 V
to 3.6 V
Min Max Unit
Test
Conditions
10 — ns Figure 20.6
10 — ns
—5
ns
—5
ns
0.4 0.6 tcyc φ ≥ 5 MHz Figure 22-2
80 — ns φ < 5 MHz
0.4 0.6 tcyc φ ≥ 5 MHz
80 — ns φ < 5 MHz
EXTAL
XTAL
Open
External clock input
(a) XTAL pin left open
EXTAL
XTAL
External clock input
(b) Complementary clock input at XTAL pin
Figure 20.6 External Clock Input Timing
Rev.6.00 Sep. 27, 2007 Page 917 of 1268
REJ09B0220-0600