D12320VF25IV Datasheet, PDF (556/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 10 16-Bit Timer Pulse Unit (TPU)
Contention between TGR Write and Compare Match: If a compare match occurs in the T₂
state of a TGR write cycle, the TGR write takes precedence and the compare match signal is
inhibited. A compare match does not occur even if the same value as before is written.
Figure 10.51 shows the timing in this case.
φ
Address
TGR write cycle
T₁
T₂
TGR address
Write signal
Compare
match signal
TCNT
Inhibited
N
N+1
TGR
N
M
TGR write data
Figure 10.51 Contention between TGR Write and Compare Match
Rev.6.00 Sep. 27, 2007 Page 524 of 1268
REJ09B0220-0600