D12320VF25IV Datasheet, PDF (500/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 10 16-Bit Timer Pulse Unit (TPU)
Bit 3 Bit 2 Bit 1 Bit 0
Channel IOC3 IOC2 IOC1 IOC0 Description
3
0000
TGR3C Output disabled
(Initial value)
1
1
0
is output _{Initial output is 0 0 output at compare match}
compare
register*¹
output
1 output at compare match
1
Toggle output at compare
match
100
Output disabled
1
10
Initial output is 1 0 output at compare match
output
1 output at compare match
1
Toggle output at compare
match
1000
1
1*
TGR3C Capture input
is input source is
capture TIOCC3 pin
register^*1
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
1
*
*
Capture input Input capture at TCNT4 count-
source is channel up/count-down
4/count clock
*: Don’t care
Note: 1. When the BFA bit in TMDR3 is set to 1 and TGR3C is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Rev.6.00 Sep. 27, 2007 Page 468 of 1268
REJ09B0220-0600