D12320VF25IV Datasheet, PDF (215/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Bus Controller
6.5 DRAM Interface (Not supported in the H8S/2321)
6.5.1 Overview
When the chip is in advanced mode, external space areas 2 to 5 can be designated as DRAM
space, and DRAM interfacing performed. With the DRAM interface, DRAM can be directly
connected to the chip. A DRAM space of 2, 4, or 8 Mbytes can be set by means of bits RMTS2 to
RMTS0 in BCRH. Burst operation is also possible, using fast page mode.
6.5.2 Setting DRAM Space
Areas 2 to 5 are designated as DRAM space by setting bits RMTS2 to RMTS0 in BCRH. The
relation between the settings of bits RMTS2 to RMTS0 and DRAM space is shown in table 6.5.
Possible DRAM space settings are: one area (area 2), two areas (areas 2 and 3), and four areas
(areas 2 to 5).
Table 6.5 Settings of Bits RMTS2 to RMTS0 and Corresponding DRAM Spaces
RMTS2
0
RMTS1
0
1
RMTS0
1
0
1
Area 5
Normal space
Normal space
DRAM space
Area 4
Area 3
Area 2
DRAM space
DRAM space
Rev.6.00 Sep. 27, 2007 Page 183 of 1268
REJ09B0220-0600