D12320VF25IV Datasheet, PDF (305/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 7 DMA Controller (Not Supported in the H8S/2321)
7.5.7 Block Transfer Mode
In block transfer mode, transfer is performed with channels A and B used in combination. Block
transfer mode can be specified by setting the FAE bit in DMABCR and the BLKE bit in
DMACRA to 1.
In block transfer mode, a transfer of the specified block size is carried out in response to a single
transfer request, and this is executed the specified number of times. The transfer source is
specified by MARA, and the transfer destination by MARB. Either the transfer source or the
transfer destination can be selected as a block area (an area composed of a number of bytes or
words).
Table 7.11 summarizes register functions in block transfer mode.
Table 7.11 Register Functions in Block Transfer Mode
Register
23
MARA
Function
0 Source address
register
Initial Setting
Start address of
transfer source
Operation
Incremented/decremented
every transfer, or fixed
23
MARB
0 Destination
Start address of Incremented/decremented
address register transfer destination every transfer, or fixed
7
0 Holds block
ETCRAH ^size
Block size
Fixed
Block size
7
0 counter
ETCRAL
15
ETCRB
0 Block transfer
counter
Legend:
MARA: Memory address register A
MARB: Memory address register B
ETCRA: Execute transfer count register A
ETCRB: Execute transfer count register B
Block size
Number of block
transfers
Decremented every
transfer; ETCRH value
copied when count reaches
H'00
Decremented every block
transfer; transfer ends
when count reaches
H'0000
Rev.6.00 Sep. 27, 2007 Page 273 of 1268
REJ09B0220-0600