D12320VF25IV Datasheet, PDF (727/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 15 Smart Card Interface
Powering On: To secure the clock duty from power-on, the following switching procedure should
be followed.
[1] The initial state is port input and high impedance. Use a pull-up resistor or pull-down resistor
to fix the potential.
[2] Fix the SCK pin to the specified output level with the CKE1 bit in SCR.
[3] Set SMR and SCMR, and switch to smart card mode operation.
[4] Set the CKE0 bit in SCR to 1 to start clock output.
15.3.8 Operation in Block Transfer Mode
Operation in block transfer mode is the same as in SCI asynchronous mode, except for the
following points. For details, see section 14.3.2, Operation in Asynchronous Mode.
Data Format: The data format is 8 bits with parity. There is no stop bit, but there is a guard time
of 2 or more bits (1 or more bits in reception).
Also, except during transmission (with start bit, data bits, and parity bit), the transmission pins go
to the high-impedance state, so the signal lines must be fixed high with a pull-up resistor.
Transmit/Receive Clock: Only an internal clock generated by the built-in baud rate generator can
be used as the transmit/receive clock. The number of basic clock periods in a 1-bit transfer interval
can be set to 32, 64, 372, or 256 with bits BCP1 and BCP0. For details, see section 15.3.5, Clock.
ERS (FER) Flag: As with the normal smart card interface, the ERS flag indicates the error signal
status, but since error signal transmission and reception is not performed, this flag is always
cleared to 0.
Rev.6.00 Sep. 27, 2007 Page 695 of 1268
REJ09B0220-0600