D12320VF25IV Datasheet, PDF (912/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 19 ROM
Write pulse application subroutine
Sub-routine write pulse
Enable WDT
Set PSU1 (2) bit in FLMCR1 (2)
Wait (y) μs
*6
Set P1 (2) bit in FLMCR1 (2)
Wait (z1) μs or (z2) μs or (z3) μs *5 *6
Clear P1 (2) bit in FLMCR1 (2)
Wait (α) μs
*6
Clear PSU1 (2) bit in FLMCR1 (2)
Wait (β) μs
*6
Disable WDT
Start of programming
Start
Set SWE1 (2) bit in FLMCR1 (2)
Wait (x) μs
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
*6
Store 128-byte program data in program
data area and reprogram data area
*4
n=1
m=0
Write 128-byte data in RAM reprogram _*1
data area consecutively to flash memory
Sub-routine-call
Write pulse
(z1) μs or (z2) μs
See Note 7 for pulse width
*6
Set PV1 (2) bit in FLMCR1 (2)
End sub
Wait (γ) μs
*6
Note 7: Write Pulse Width *6
Number of Writes (n) Write Time (z) μs
1
z1
2
z1
3
z1
4
z1
5
z1
6
z1
7
z2
8
z2
9
z2
10
z2
11
z2
12
z2
1...3
z...2
998
z2
999
z2
1000
z2
Note: Use a (z3) µs write pulse for additional
programming.
RAM
Program data area
(128 bytes)
Reprogram data area
(128 bytes)
Increment address
H'FF dummy write to verify address
Wait (ε) μs
*6
Read verify data
*2
Read data = verify
NG
data?
OK
NG
6≥n?
OK
Additional program data computation
m=1
Transfer additional program data to
additional program data area
*4
Reprogram data computation
*3
Transfer reprogram data to reprogram _*4
data area
128-byte
data verification
NG
completed?
OK
Clear PV1 (2) bit in FLMCR1 (2)
Wait (η) μs
*6
n←n+1
Additional program data
area (128 bytes)
NG
6≥n?
OK
Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first
address written to must be H'00 or H'80. A 128-byte data transfer must
be performed even if writing fewer than 128 bytes; in this case, H'FF
data must be written to the extra addresses.
2. Verify data is read in 16-bit (W) units.
3. Even bits for which programming has been completed in the 128-byte
programming loop will be subjected to additional programming if they
fail the subsequent verify operation.
4. A 128-byte area for storing program data, a 128-byte area for storing
reprogram data, and a 128-byte area for storing additional program data
Sequentially write 128-byte data in
additional program data area in RAM to *1
flash memory
Write Pulse
(z3) µs additional write pulse
NG
m = 0?
OK
Clear SWE1 (2) bit in FLMCR1 (2)
*6
*6
n ≥ N?
NG
OK
Clear SWE1 (2) bit in FLMCR1 (2)
should be provided in RAM. The contents of the reprogram data and
additional program data areas are modified as programming proceeds.
Wait (θ) μs
*6
Wait (θ) μs
*6
5. A write pulse of (z1) or (z2) μs should be applied according to the progress
of programming. See Note 7 for the pulse widths. When the additional program
End of programming
Programming failure
data is programmed, a write pulse of (z3) μs should be applied. Reprogram data X' stands for reprogram data to which a write pulse has been applied.
6. For the values of x, y, z1, z2, z3, α, β, γ, ε, η, θ, and N, see section 22.2.6, Flash Memory Characteristics.
Program Data Operation Chart
Original Data Verify Data Reprogram Data
(D)
(V)
(X)
Comments
0
0
1
1
0
1
1
Programming completed
0
Programming incomplete; reprogram
1
Still in erased state; no action
Additional Program Data Operation Chart
Reprogram Verify Data Additional
Data (X')
(V) Program Data (Y)
Comments
0
0
1
1
0
1
0
Additional programming executed
1
Additional programming not executed
Additional programming not executed
Additional programming not executed
Figure 19.71 Program/Program-Verify Flowchart
Rev.6.00 Sep. 27, 2007 Page 880 of 1268
REJ09B0220-0600