D12320VF25IV Datasheet, PDF (1219/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Appendix B Internal I/O Registers
PFCR2—Port Function Control Register 2
H'FFAC
Ports
Bit
:
7
6
5
4
3
2
1
0
WAITPS BREQOPS CS167E CS25E ASOD —
—
—
Initial value :
0
0
1
1
R/W
0
0
0
Read/Write : _R/W
R/W
R/W
R/W
R
R
R
AS Output Disable
0 PF₆ is designated as AS output pin
1 PF₆ is designated as I/O port, and
does not function as AS output pin
Note: This bit is valid in modes 4 to 6.
CS25 Enable
0 CS₂, CS₃, CS₄, and CS₅ output disabled
(can be used as I/O ports)
1 CS₂, CS₃, CS₄, and CS₅ output enabled
Note: Clear the DDR bits to 0 before changing
the CS25E setting.
CS167 Enable
0 CS₁, CS₆, and CS₇ output disabled
(can be used as I/O ports)
1 CS₁, CS₆, and CS₇ output enabled
Note: Clear the DDR bits to 0 before changing
the CS167E setting.
BREQO Pin Select
0 BREQO output is PF₂ pin
1 BREQO output is P5₃ pin
Note: Set BREQOPS before setting
the BREQOE bit in BCRL to 1.
WAIT Pin Select
0 WAIT input is PF₂ pin
1 WAIT input is P5₃ pin
Note: Set WAITPS before setting
the WAITE bit in BCRL to 1.
Rev.6.00 Sep. 27, 2007 Page 1187 of 1268
REJ09B0220-0600